Volantis Raises $88M Series A to Fix AI Memory Bottlenecks

Volantis has secured an $88 million Series A funding round to commercialize photonic interconnect technology designed to overcome the AI memory wall for high-performance inference, bringing its total capital raised to $97 million according to a PR Newswire release.

The financing was co-led by investors Lachy Groom and Abstract Ventures. The capital targets the physical limitations of electrical wiring in data centers, which struggle to move data quickly enough between processors and high-capacity memory banks during large-scale model operations.

"As AI agents take on more work, how fast they complete that work will increasingly determine how fast companies can operate," said Tapa Ghosh, CEO and co-founder of Volantis, in a statement regarding the funding. "Today's hardware forces a tradeoff between running the largest, most sophisticated models and running them fast. We started Volantis to eliminate that tradeoff."

The A-1 Photonic Architecture

The startup's primary system, designated the A-1, utilizes optical interconnects rather than traditional copper traces to transmit data using light particles. According to technical specifications provided by Volantis, the architecture is engineered to execute models exceeding 20 trillion parameters at speeds up to 10,000 tokens per second per individual user.

By replacing electrical signals with optics within the chip packaging and board level, the company aims to lower the financial and energetic cost per generated token. This performance target addresses the operational constraint facing enterprise deployments of generative models: the latency introduced when fetching weights from external dynamic random-access memory.

Commercialization and Delivery Timeline

Following the close of the Series A round, Volantis has scheduled initial shipments of its integrated inference engines to commercial customers in 2027. The development timeline involves scaling manufacturing partnerships for its proprietary photonic components ahead of pilot deployments.

What the Memory Wall Means for AI Infrastructure

The hardware bottleneck known as the memory wall occurs because processor computing speeds have outpaced memory bandwidth improvements. As frontier models scale into trillions of parameters, shifting parameters off-chip creates severe idle time for arithmetic logic units.

Photonic interconnects attempt to bypass this limitation by routing data through optical waveguides, offering higher bandwidth density and lower energy consumption per bit transferred than copper wires. Startups in the optical computing sector are competing to establish commercial viability as enterprise data centers search for alternatives to conventional silicon scaling limitations.