ASML Partners With Chipmakers to Adapt High NA EUV Tools for 2033

ASML is partnering with major global chipmakers to adapt its next-generation High NA EUV lithography tools for larger mask sizes, clearing a major technical hurdle required to manufacture massive data center processors by the early 2030s, according to an Investing.com report.

"If we’re going to pull it off as an industry, then you’ll actually see that the productivity of those systems will go up by 40%," said Marco Pieters, ASML’s Chief Technology Officer, in a statement regarding the partnership.

Overcoming Size Limits for Data Center Chips

The initiative addresses a fundamental limitation in current manufacturing equipment. ASML plans to transition toward larger mask dimensions that enable its newest High NA tools to print dies measuring up to approximately 800 square millimeters. Current equipment configurations restrict reticle sizes, making it difficult to produce monolithic processors matching the scale of today's largest artificial intelligence and data center accelerators without stitching multiple dies together.

Under the newly outlined roadmap, ASML intends to demonstrate a functional pilot production line utilizing the larger masks by 2031. Full commercial readiness for high-volume manufacturing with the updated systems is scheduled to follow by 2033.

Adoption Timelines Across Major Semiconductor Manufacturers

Deployment status and commercialization targets vary significantly across the industry's primary fabrication houses:

• Intel: Currently utilizes ASML's newest High NA EUV systems for early-stage and laptop chip development, serving as an early adopter of the technology.
• Samsung Electronics: Plans to integrate High NA EUV technology into high-volume memory chip production for DRAM by 2028.
• SK Hynix: Currently participating in preliminary consortium discussions regarding 12-inch masks, targeting 2028 to incorporate High NA EUV equipment into DRAM mass production.
• TSMC: Has established a target to deploy High NA technology in advanced-node high-volume production starting in 2030, though the tools are not yet active for high-volume runs at Taiwan Semiconductor Manufacturing or Samsung.

What Is at Stake for Advanced Node Fabrication

Transitioning the semiconductor supply chain to larger masks on High NA platforms represents a critical evolutionary step for sub-2nm node manufacturing. As hyperscalers and artificial intelligence developers demand increasingly powerful processors with higher transistor budgets, equipment manufacturers and foundries must align their multi-year capital expenditure roadmaps to resolve optical field-of-view constraints before commercial scaling accelerates in the next decade.